#acl UserGroup:read,write,revert,delete All:read

== DOCUMENTATION ==

Thèse de Zied Marrakchi sur les FPGAs en arbre :
"EXPLORATION AND OPTIMIZATION OF TREE-BASED FPGA ARCHITECTURES" : [[attachment:Phd_Zied.pdf||&do=get]]

Poster présenté à la 3ème convention du pôle System@tic : [[attachment:SEFPGA.pdf||&do=get]]

=== Bibliographie ===

- Routing architectures for hierarchical field programmable gate arrays. 
A.Agarwal and Lewis D. 
In Proceedings 1994 IEEE International Conference on Computer Design, pages 475–478.

- Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don’t reallywant 100%LUT utilization).
A.DeHon  
Proceedings 1999 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Montery, CA.

- Compact Multilayer Layout for Butterfly Fat-Tree.
A.DeHon. 
ACM Symposium on Parallel Algorithms and Architectures, pages 206–215. Bar Harbor, Maine, USA.2000.

 - Rent’s Rule Based Switching Requirements. 
A.DeHon. 
System Level Interconnect Prediction Workshop(SLIP). CA, 2001.

- Unifing Mesh and Tree-Based Programmable Interconnect.
A.DeHon  
IEEE Transactions on VLSI Systems, (12):10, 2004

- Fat-trees: Universal networks for hardware efficient
C.Leiserson 
supercomputing. IEEE Transactions on Computers, C-34(10):892–901, 1985.

- HSRA: High Speed, Hierarchical Synchronous Reconfigurable Array
William Tsu, Kip Macy, Atul Joshi, Ramy Huang, Norman Walker, Tony Tung, Omid Rowhani, Varghese George, John Wawrzynek, Andre DeHon. 
Proceedings of the International Symposium on Field Programmable Gate Arrays, 20(1469-1479):125–134. 1999.

- Hierarchical Interconnection Structures for Field Programmable Gate Arrays. 
Y.Lay and P.Wang 
IEEE Transactions on VLSI Systems,5(2):186–196. 1997